Semiconductor memory device having reduced current consumption at internal boosted potential

ABSTRACT

In a three-state circuit issuing a shared gate signal, after an N-channel MOS transistor charges a node issuing an output signal OUT to external power supply potential exvdd, the N-channel MOS transistor is turned off, and a P-channel MOS transistor is turned on to charge the node to boosted potential VPP. Thereby, a power consumed at boosted potential VPP can be reduced, and sizes of transistors of a VPP generating circuit can be reduced. Thereby, a semiconductor memory device having a small chip size can be achieved.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,and particularly a semiconductor memory device having a memory cellarray of a shared sense amplifier type.

[0003] 2. Description of the Background Art

[0004] In a Dynamic Random Access Memory (DRAM), a boosted potential VPPis used for driving signal lines bearing large loads when reading datafrom a memory array, and more specifically for driving a word line, abit line equalize signal line (BLEQ) and a shared gate signal line (BLI)of a memory cell array of a shared sense amplifier type, which will bedescribed later. Gate circuits which are connected to these signal linesemploy N-channel MOS transistors. For transmitting a power supplypotential, which is applied to a source of the N-channel MOS transistor,to a drain, it is necessary to apply a H-level, which is higher than thepower supply potential by at least an amount corresponding to athreshold voltage, as a gate potential. Therefore, boosted potential VPPis required.

[0005]FIG. 17 shows boosted potential VPP which is internally generated.

[0006] Referring to FIG. 17, boosted potential VPP is generated by a VPPgenerating circuit arranged within a semiconductor memory device. In VPPgenerating circuit, an external power supply potential exvdd which isexternally supplied to the semiconductor memory device is boosted by abooster circuit such as a charge pump circuit or the like, and therebyboosted potential VPP is generated.

[0007] In recent years, however, external power supply potential exvddhas been lowered to increase a potential difference from requiredboosted potential VPP. Since VPP generating circuit boosts externalpower supply potential exvdd, which is low, by a charge pump or thelike, increase in power consumption at boosted potential VPP requiresthe charge pump to be formed of transistors having increased sizes.Thereby, the chip area of the semiconductor memory device increases.

[0008] In the prior art, therefore, it has been necessary to devise astructure and/or a method for suppressing the power consumption atboosted potential VPP.

[0009]FIG. 18 is a circuit diagram showing a structure of a three-statecircuit which is used in the prior art for suppressing power consumptionat boosted potential VPP.

[0010] Referring to FIG. 18, this three-state circuit includes aP-channel MOS transistor PQ which is connected between a node receivingboosted potential VPP and an output node NOUT, and receives on its gatea signal A, an N-channel MOS transistor NQ which is connected betweenoutput node NOUT and a ground node, and receives on its gate a signal B,and an N-channel MOS transistor NQ 1 which is connected between a nodereceiving external power supply potential exvdd and output node NOUT,and receives on its gate a control signal C.

[0011] For changing the output from 0 V to boosted potential VPP, thisthree-state circuit operates in such a manner that output node NOUT isboosted from 0 V to external power supply potential exvdd in a firststage, and then the potential on output node NOUT is boosted externalpower supply potential exvdd to boosted potential VPP in the secondstage. In this manner, the power which is consumed at boosted potentialVPP generated by VPP generating circuit can be merely equal to thatrequired for boosting the potential from external power supply potentialexvdd to boosted potential VPP.

[0012]FIG. 19 is an operation waveform diagram showing an operation ofthe three-state circuit shown in FIG. 18.

[0013] Referring to FIGS. 18 and 19, the potential of signal A changesfrom 0 V to boosted potential VPP at time t1, the potential of signal Bchanges from 0 V to boosted potential VPP and the potential of controlsignal C changes from external power supply potential exvdd to theground potential. Thereby, P- and N-channel MOS transistors PQ and NQ 1are turned off, and N-channel MOS transistor NQ is turned on so thatoutput node NOUT is coupled to the ground node. Therefore, output signalOUT lowers to L-level.

[0014] At a time t2, the potential of signal B falls from boostedpotential VPP to the ground potential, and the potential of controlsignal C rises from the ground potential to external power supplypotential exvdd. Thereby, N-channel MOS transistor NQ is turned off, andN-channel MOS transistor NQ1 is turned on so that output node NOUT iscoupled to external power supply potential exvdd by N-channel MOStransistor NQ1. However, the gate potential of N-channel MOS transistorNQ1 is equal to external power supply potential exvdd. Therefore,voltage drop by an amount equal to threshold voltage Vth occurs. For aperiod between t2 and t3, therefore, output node NOUT is charged toattain a potential which is lower than external power supply potentialexvdd by an amount equal to the threshold voltage.

[0015] At a time t3, the potential of signal A lowers from boostedpotential VPP to L-level. Thereby, P-channel MOS transistor PQ is turnedon, and output node NOUT is coupled to boosted potential VPP. Therefore,the potential of signal OUT rises from a value of (exvdd-Vth) to boostedpotential VPP after time t3. Thereby, the power consumption at boostedpotential VPP generated by the VPP generating circuit is merely causedby the boosting after time t3.

[0016] However, the potential difference between boosted potential VPPand external power supply potential exvdd has been considerablyincreased in accordance with lowering of the external power supplypotential. Therefore, the potential on the output node is raised by alarge amount after time t3 so that the effect of reducing the powerconsumption at boosted potential VPP has been reduced.

[0017] For increasing the effect of reducing the power consumption whilepreventing the potential from lowering by the magnitude corresponding tothreshold voltage Vth, the potential of control signal C at H-level canbe equal to boosted potential VPP. In this case, however, P- andN-channel MOS transistors PQ and NQ1 couple boosted potential VPP toexternal power supply potential exvdd when output node NOUT is coupledto boosted potential VPP by P-channel MOS transistor PQ. Thereby, leakfrom boosted potential VPP to external power supply potential exvddoccurs.

SUMMARY OF THE INVENTION

[0018] An object of the invention is to provide a semiconductor memorydevice, in which power consumption at boosted potential VPP is reducedso that sizes of transistors contained in a VPP generating circuit andtherefore a chip area can be small.

[0019] In summary, the invention provides a semiconductor memory deviceincluding a memory cell array, a voltage generating circuit, a firstinternal node, a first control circuit and a first drive circuit.

[0020] The memory cell array includes a plurality of memory cellsarranged in rows and columns for storing externally applied data. Thevoltage generating circuit receives and boosts an externally appliedfirst power supply potential to generate a second power supply potentialto be used for data transmission with respect to the memory cell array.The first internal node is activated by the second power supplypotential. The first control circuit issues first and second controlsignals for driving the first internal node in accordance with anexternally applied input signal. The first control circuit activates thefirst control signal for a predetermined time in accordance with changein the input signal, and activates the second control signal uponelapsing of the predetermined time after the change in the input signal.The first drive circuit receives the first and second power supplypotentials, and drives the potential on the first internal node to thesecond power supply potential in accordance with the first and secondcontrol signals. The first drive circuit includes a first switch circuitto be turned on to couple the first power supply potential to the firstinternal node in accordance with the first control signal, and a secondswitch circuit to be turned on to couple the second power supplypotential to the first internal node in accordance with the secondcontrol signal.

[0021] According to another aspect, the invention provides asemiconductor memory device including a memory cell array, a voltagegenerating circuit and a first drive circuit.

[0022] The memory cell array includes a plurality of memory cellsarranged in rows and columns for storing externally applied data. Thevoltage generating circuit receives and boosts an externally appliedfirst power supply potential to generate a second power supply potentialto be used for data transmission with respect to the memory cell array.The first drive circuit receives the first and second power supplypotentials and a ground potential, and drives a potential on a firstinternal node in accordance with an externally applied input signal. Thefirst drive circuit activates the potential on the first internal nodeto attain the second power supply potential when the input signalindicates access to a first region in the memory cell array, deactivatesthe potential on the first internal node to attain the ground potentialwhen the input signal indicates access to a second region in the memorycell array, and couples the potential on the first internal node to thefirst power supply potential when the input signal does not indicate theaccess to the memory cell array.

[0023] Accordingly, the invention can achieve such an advantage that thepower consumption at a boosted potential can be suppressed, and therebysizes of a voltage generating circuit for generating the boostedpotential and therefore a chip size can be reduced.

[0024] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a schematic block diagram showing a whole structure of asemiconductor memory device 1 according to the invention;

[0026]FIG. 2 is a block diagram showing a structure of a control signalgenerating portion included in a row decoder 26 shown in FIG. 1;

[0027]FIG. 3 is a circuit diagram showing a structure of a controlcircuit 42 shown in FIG. 2;

[0028]FIG. 4 is a circuit diagram showing a structure of a levelconverting circuit 66 shown in FIG. 3;

[0029]FIG. 5 is a circuit diagram showing a structure of a three-statecircuit 44 shown in FIG. 2;

[0030]FIG. 6 is a circuit diagram showing a structure of a portion of amemory cell array of a shared sense amplifier type, and morespecifically a connection portion between a memory cell array 32 and asense amplifier 30 shown in FIG. 1;

[0031]FIG. 7 is an operation waveform diagram showing an operation ofthree-state circuit 44;

[0032]FIG. 8 shows a problem of a transistor of the three-state circuitin the first embodiment;

[0033]FIG. 9 is a circuit diagram showing a structure of a three-statecircuit 44 a used in a second embodiment;

[0034]FIG. 10 is an operation waveform diagram showing an operation ofthree-state circuit 44 a shown in FIG. 9;

[0035]FIG. 11 is a block diagram showing a structure of a control signalgenerating portion included in a row decoder used in a third embodiment;

[0036]FIG. 12 is a circuit diagram showing a structure of a controlcircuit 122 shown in FIG. 11;

[0037]FIG. 13 is an operation waveform diagram showing an operation of athird embodiment;

[0038]FIG. 14 is a circuit diagram showing a structure of a controlcircuit 122 a in a fourth embodiment;

[0039]FIG. 15 is an operation waveform diagram showing an operation of athree-state circuit in the case of use of control circuit 122 a;

[0040]FIG. 16 is an operation waveform diagram showing a data readoperation in the fourth embodiment;

[0041]FIG. 17 shows a boosted potential VPP which is internallygenerated;

[0042]FIG. 18 is a circuit diagram showing a structure of a three-statecircuit, which is used in the prior art for suppressing a powerconsumption at boosted potential VPP; and

[0043]FIG. 19 is an operation waveform diagram for showing an operationof a three-state circuit in FIG. 18.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Embodiments of the invention will now be described in greaterdetail with reference to the drawings. In the figures, the same orcorresponding portions bear the same reference numbers.

[0045] [First Embodiment]

[0046]FIG. 1 is a schematic block diagram showing a whole structure of asemiconductor memory device 1 according to the invention.

[0047] Referring to FIG. 1, semiconductor memory device 1 includescontrol signal input terminals 2, 4 and 6 which receive control signalsExt./RAS, Ext./CAS and Ext./WE, respectively, an address input terminalgroup 8, a terminal group 14 for input/output of data signals DQ0-DQn, aground terminal 12 supplied with a ground potential Vss, and a powersupply terminal 10 supplied with external power supply potential exvdd.

[0048] Semiconductor memory device 1 further includes a clock generatingcircuit 22, a row and column address buffer 24, a row decoder 26, acolumn decoder 28, a sense amplifier pulse I/O-control circuit 30, amemory cell array 32, a gate circuit 18, a data input buffer 20 and adata output buffer 34.

[0049] Clock generating circuit 22 controls a whole operation of thesemiconductor memory device by issuing a control clock which correspondsto a predetermined operation mode based external row address strobesignal Ext./RAS and external column address strobe signal Ext./CAS,which are externally supplied via control signal input terminals 2 and4, respectively.

[0050] Row and column address buffer 24 applies the address signals,which are produced based on externally applied address signals A0-Ai (i:natural number), to row and column decoders 26 and 28.

[0051] Data signals DQ0-DQn can be externally sent from or to the memorycell in memory cell array 32, which is designated by row and columndecoders 26 and 28, through I/O terminal 14 as well as sense amplifierplus I/O control circuit 30 and data I/O buffer 20 (or data outputbuffer 34).

[0052] Semiconductor memory device 1 further includes a VPP generatingcircuit 36, which generates boosted potential VPP by receiving andboosting external power supply potential exvdd applied to power supplypotential 10. Boosted potential VPP is supplied to memory cell array 32and sense amplifier plus I/O control circuit 30 as a drive potential ofa gate circuit, which is provided for isolating the bit line of thememory array of the shared sense amplifier structure type describedlater from the sense amplifier.

[0053] Semiconductor memory device 1 shown in FIG. 1 is a typicalexample, and the invention can also be applied, e.g., to a synchronoussemiconductor memory device (SDRAM).

[0054]FIG. 2 is a block diagram showing a structure of a control signalgenerating portion included in row decoder 26 shown in FIG. 1.

[0055] Referring to FIG. 2, the control signal generating portionincludes a control circuit 42 which receives a block select signal BLKR,and issues control signals AL, BL and CL, a three-state circuit 44 whichreceives control signals AL, BL and CL, and issues a shared gate signalBLIL, a control circuit 46 which receives a block select signal BLKL,and issues control signals AR, BR and CR, and a three-state circuit 48which receives control signals AR, BR and CR, and issues shared gatesignal BLIR.

[0056]FIG. 3 is a circuit diagram showing a structure of control circuit42 shown in FIG. 2.

[0057] Referring to FIG. 3, control circuit 42 includes a delay circuit52 which receives and delays block select signal BLK by a predeterminedtime, an NOR circuit 54 which receives block select signal BLK and theoutput of delay circuit 52, a level converting circuit 56 which receivesthe output of NOR circuit 54, and converts the level thereof to issuecontrol signal A, inverters 58 and 62 which receive and invert blockselect signal BLK, a level converting circuit 60 which receives theoutput of inverter 58, and converts the level thereof to issue controlsignal B, an AND circuit 64 which receives the outputs of delay circuit52 and inverter 62, and a level converting circuit 66, which receivesthe output of AND circuit 64 and converts the level thereof to issuecontrol signal C.

[0058] Block select signal BLKR and control signals AL, BL and CL shownin FIG. 2 correspond to block select signal BLK and control signals A, Band C in FIG. 3, respectively.

[0059] Control circuit 46 shown in FIG. 2 has the substantially samestructure as control circuit 42, and thereof description thereof is notrepeated. In this case, block select signal BLKL and control signals AR,BR and CR shown in FIG. 2 correspond to block select signal BLK andcontrol signals A, B and C in FIG. 3, respectively.

[0060]FIG. 4 is a circuit diagram showing a structure of levelconverting circuit 66 shown in FIG. 3.

[0061] Referring to FIG. 4, level converting circuit 66 includes aninverter 72 which receives and inverts an input signal IN, an N-channelMOS transistor 76 which is connected between a node N51 and the groundnode, and has a gate receiving input signal IN, a P-channel MOStransistor 74 which is connected between a node supplied with boostedpotential VPP and node N51, and has a gate connected to a node N52, anN-channel MOS transistor 80 which is connected between node N52 and theground node, and has a gate receiving the output of inverter 72, and aP-channel MOS transistor 78 which is connected between a node suppliedwith boosted potential VPP and node N52, and has a gate connected tonode N51. Output signal OUT of level converting circuit 66 is issuedfrom node N52.

[0062] Level converting circuits 56 and 60 shown in FIG. 3 have thesubstantially same structures as level converting circuit 66 shown inFIG. 4, and therefore description thereof is not repeated.

[0063]FIG. 5 is a circuit diagram showing a structure of three-statecircuit 44 shown in FIG. 2.

[0064] Referring to FIG. 5, three-state circuit 44 includes a P-channelMOS transistor 92 which is connected between a node supplied withboosted potential VPP and a node N53, and has a gate receiving controlsignal A, an N-channel MOS transistor 94 which is connected between nodeN53 and the ground node, and has a gate receiving control signal B, andan N-channel MOS transistor 96 which is connected between a nodesupplied with external power supply potential exvdd and node N53, andhas a gate receiving control signal C. Output signal OUT of three-statecircuit 44 is issued from node N53.

[0065] Control signals AL, BL and CL, and shared gate signal BLIL inFIG. 2 correspond to control signals A, B and C, and output signal OUTin FIG. 5, respectively.

[0066] Three-state circuit 48 in FIG. 2 has the substantially samestructure as three-state circuit 44, and therefore description thereofis not repeated. In this case, control signals AR, BR and CR, and sharedgate signal BLIL in FIG. 2 correspond to control signals A, B and C, andoutput signal OUT in FIG. 5.

[0067]FIG. 6 is circuit diagram showing a structure of a portion of thememory cell array of the shared sense amplifier type, and morespecifically a connecting portion between memory cell array 32 and senseamplifier 30 in FIG. 1.

[0068] Referring to FIG. 6, the memory cell array of the shared senseamplifier type will now be described briefly. The memory cells aredivided into two blocks L and R, which commonly use a sense amplifierband. The sense amplifier band is disposed in the connection portionbetween blocks L and R. As described above, the addresses which are notsimultaneously accessed are divided into blocks, and the plurality ofblocks commonly use the sense amplifiers. This structure is referred toas the shared sense amplifier type of the memory cell array.

[0069] This connection portion includes a sense amplifier 102 whichexpands the potential difference between bit lines BL0 and /BL0 foroutputting it, a gate circuit 104 which connects bit lines BL0 and /BL0to bit lines BLL and /BLL, respectively, in accordance with a sharedgate signal BLIL, a gate circuit 106 which connects bit lines BL0 and/BL0 to bit lines BLR and /BLR, respectively, in accordance with ashared gate signal BLIR, an equalize circuit 108 which equalizes thepotentials on bit lines BLL and /BLL in accordance with an equalizesignal BLEQL, and an equalize circuit 110 which equalizes the potentialson bit lines BLR and /BLR in accordance with an equalize signal BLEQR.Memory cell MC is arranged at each crossing between the bit line and theword line.

[0070] Although a plurality of word lines are actually arranged in eachof blocks L and R, FIG. 6 shows only one word line and one memory cellas a typical example. Memory cell MC includes an access transistor 112which has a gate connected to the word line, and is connected betweenbit line BLL and a storage node, and a capacitor 114 which is arrangedbetween the storage node and the ground node.

[0071] Although not shown, equalize circuit 108 includes first, secondand third N-channel MOS transistors, which are usually turned on inresponse to equalize signal BLEQL. When turned on, the first N-channelMOS transistor connects bit lines BLL and /BLL together, the secondN-channel MOS transistor couples bit line BLL to cell plate potentialVCP, and couples bit line /BL to cell plate potential VCP. Equalizecircuit 110 has the substantially same structure as equalize circuit108.

[0072]FIG. 7 is an operation waveform diagram showing an operation ofthree-state circuit 44.

[0073] Referring to FIG. 7, block select signal BLKL rises from L-levelto H-level at time t1 for reading data from block L shown in FIG. 6 inaccordance with the externally applied row address. Thereby, forisolating sense amplifier 102 in FIG. 6 from block R, gate circuit 106is turned off. For issuing this shared gate signal BLIR, control circuit46 in FIG. 2 operates in response to block select signal BLKL to boostsignal AR from L-level to boosted potential VPP and boost signal BR fromthe ground potential to external power supply potential exvdd or boostedpotential VPP. In accordance with this, P-channel MOS transistor 92shown in FIG. 5 is turned off, and N-channel MOS transistor 94 is turnedon. Accordingly, shared gate signal BLIR issued from three-state circuit48 falls from boosted potential VPP to the ground potential. Thereby,gate circuit 106 is turned off, and block R is isolated from senseamplifier 102 for a period between times t1 and t2.

[0074] At subsequent time t2, block select signal BLKL falls fromH-level to L-level for returning to the standby state in accordance withcompletion of the operation of reading data from block L. In accordancewith this, control circuit 46 in FIG. 2 lowers signal BR from H-level toL-level. Control signal CR is set to H-level taking the form of pulsefor a period equal to a delay time of delay circuit 52 shown in FIG. 3.Level converting circuit 66 converts this H-level to boosted potentialVPP level as shown in FIG. 4 so that the H-level of control signal CRfor the period between times t2 and t3 is equal to boosted potentialVPP.

[0075] In the first embodiment, therefore, the output node is charged toattain external power supply potential exvdd as can be seen from awaveform W2 in contrast to the prior art, in which the charging isperformed to attain the potential lower than external power supplypotential exvdd by threshold voltage Vth as shown in a waveform W1.

[0076] At time t3, control signal AR falls from H-level to L-level inaccordance with the fact that a time equal to the delay time of delaycircuit 52 in FIG. 3 elapsed after the falling of block select signalBLKL. Also, control signal CR falls from H-level to L-level. Thereby,N-channel MOS transistor 96 in FIG. 5 is turned off, and alternatively,P-channel MOS transistor 92 is turned on. When P-channel MOS transistor92 is turned on in this manner, N-channel MOS transistor 96 is turnedoff so that a leak current does not flow from boosted potential VPP toexternal power supply potential exvdd.

[0077] Accordingly, the potential on the output node of three-statecircuit 48, which issues the shared gate signal, can be charged toexternal power supply potential exvdd by applying, as control signal CR,the pulse signal of which H-level is defined by the boosted potential.The leak current does not occur, and the power consumption at boostedpotential VPP can be merely equal to the consumption required forchanging the potential from external power supply potential exvdd toboosted potential VPP. Therefore, elements included in the circuit forgenerating boosted potential VPP can have small sizes.

[0078] In the DRAM, word lines WL in the memory array shown in FIG. 6 aswell as equalize signal lines receiving equalize signals BLEQL and BLEQRare usually driven by boosted potential VPP.

[0079] The word line is selected in accordance with the row addresssignal, and the selected word line is activated to attain boostedpotential VPP. Bit line equalize signals BLEQL and BLEQR are keptactive, and therefore at the level of boosted potential VPP for a periodimmediately before row selection according to the row address signal,and are deactivated when the word line is activated. When reading orwriting of data is completed, the word line is deactivated, and bit lineequalize signals BLEQL and BLEQR are activated again so that bit linepair is equalized for the next read or write operation. The three-statecircuit shown in FIG. 5 may be used as a drive circuit for the word lineand the equalize signal line.

[0080] In this case, the power consumption at boosted potential VPP canbe reduced so that the elements of reduced sizes can be employed in thecircuit for generating boosted potential VPP.

[0081] [Second Embodiment]

[0082]FIG. 8 shows a problem of the transistor in the three-statecircuit of the first embodiment.

[0083] Referring to FIG. 8, three-state circuit 44 uses an N-channel MOStransistor 96 for charging output node N53. In N-channel MOS transistor96, a large potential difference (Vb−s) is present between the substratepotential and the source potential.

[0084] In recent years, the concentration of implanted impurities in thetransistor has been increased in accordance with reduction in sizes. Ingeneral, as the potential difference between the substrate and thesource increases, the substrate bias effect increases the thresholdvoltage of the transistor. The threshold voltage increases in proportionto the substrate bias effect, and the constant of this proportionalitytends to increase as the concentration of implanted impuritiesincreases. The structure in which the N-channel MOS transistor isemployed as the transistor for charging node N53 as shown in FIG. 8 maycause such a problem that the charged voltage on node N53 is lowered byan amount equal to the increased amount of the threshold voltage if theactive potential of control signal C is not sufficiently high.

[0085]FIG. 9 is a circuit diagram showing a structure of a three-statecircuit 44 a used in the second embodiment.

[0086] Referring to FIG. 9, three-state circuit 44 a differs fromthree-state circuit 44 in the first embodiment in that a P-channel MOStransistor 96 a is employed instead of N-channel MOS transistor 96.P-channel MOS transistor 96 a has a gate receiving control signal C, andis connected between node N53 and a node supplied with external powersupply potential exvdd. Other structures are the same as those ofthree-state circuit 44, and therefore description thereof is notrepeated.

[0087] Control signal C in the second embodiment is formed of aninverted signal of control signal C in the first embodiment. In thiscase, a back gate of P-channel MOS transistor 96 a is coupled to boostedpotential VPP. Since external power supply potential exvdd is smallerthan boosted potential VPP, leak of a current from the source ofP-channel MOS transistor 96 a to the back gate does not occur. Even whenP-channel MOS transistor 92 couples node N53 to boosted potential VPP,the leak current does not flow from node N53 to the back gate ofP-channel MOS transistor 96 a because both the potentials on node N53and the back gate of P-channel MOS transistor 96 a are equal to VPP, andno potential difference is present between them.

[0088]FIG. 10 is an operation waveform diagram showing an operation ofthree-state circuit 44 a shown in FIG. 9.

[0089] Control signals AR and BR have the same waveforms as thosealready described in FIG. 7, and description thereof is not repeated.

[0090] Control signal CR has an inverted waveform of control signal CRshown in FIG. 7. The inverted waveform can be produced by adding aninverter to the output of level converting circuit 66 shown in FIG. 3.Node N51 shown in FIG. 4 may be used as an inverted output.

[0091] Control signal CR falls from H-level to L-level at time t2, andrises from L-level to H-level at time t3. Thereby, the potential whichis placed on node N53 by charging for a period between times t2 and t3does not lower by an amount equal to the threshold voltage, and thecharging can be performed until the potential reaches external powersupply potential exvdd. Therefore, the second embodiment can likewisereduce the power consumed at boosted potential VPP.

[0092] [Third Embodiment]

[0093]FIG. 11 is a block diagram showing a structure of a control signalgenerating portion included in a row decoder used in a third embodiment.

[0094] Referring to FIG. 11, the control signal generating portion ofthe third embodiment includes a control circuit 122 which receives blockselect signals BLKL and BLKR produced in accordance with the row addresssignal, and issues control signals, AL, BL and CL, a three-state circuit124 which receives control signals AL, BL and CL, and issues shared gatesignal BLIL, a control circuit 126 which receives block select signalsBLKL and BLKR, and issues control signals AR, BR and CR, and athree-state circuit 128 which receives control signals AR, BR and CR,and issues shared gate signal BLIR.

[0095]FIG. 12 is a circuit diagram showing a structure of controlcircuit 122 shown in FIG. 11.

[0096] Referring to FIG. 12, control circuit 122 includes an inverter132 which receives and inverts a block select signal BLK1, a levelconverting circuit 134 which receives the output of inverter 132, andconverts the level thereof to issue control signal A, a level convertingcircuit 136 which receives a block select signal BLK2, and converts thelevel thereof to issue control signal B, an inverter 138 which receivesand inverts block select signal BLK2, an NAND circuit 140 which receivesthe outputs of NAND circuit 132 and inverter 138, and a level convertingcircuit 142 which receives the output of NAND circuit 140, and convertsthe level thereof to issue control signal C.

[0097] Control circuit 122 receives block select signal BLKL as blockselect signal BLK1, and also receives block select signal BLKR as blockselect signal BLK2. Control signals A, B and C are issued as controlsignals AL, BL and CL in FIG. 11, respectively.

[0098] Since the control circuit 126 in FIG. 11 has the substantiallysame structure as control circuit 122, description thereof is notrepeated. Control circuit 126 receives block select signal BLKR as blockselect signal BLK1, and also receives block select signal BLKL as blockselect signal BLK2. Control signals A, B and C are issued as controlsignals AR, BR and CR in FIG. 11, respectively.

[0099] Level converting circuits 134, 136 and 142 have the substantiallysame structures as level converting circuit 136 shown in FIG. 4, andtherefore description thereof is not repeated.

[0100]FIG. 13 is an operation waveform diagram showing an operation ofthe third embodiment.

[0101] According to the structures shown in FIGS. 11 and 12, thepotential of the shared gate signal is set to external power supplypotential exvdd while the block is not selected, and in other words, forthe standby periods before time t1 in FIG. 13, between times t2 and t3,and after time t4. Thereby, the current consumption at boosted potentialVPP during standby can be reduced. The block select signal is issuedbased on the row address applied to the row decoder. At time t1, blockselect signal BLKL is activated so that shared gate signal BLIL attainsboosted potential VPP, and shared gate signal BLIR attains the groundpotential. In time t3, when block select signal BLKR is activated,shared gate signal BLIR attains boosted potential VPP, and shared gatesignal BLIL attains the ground potential. Thereby, the signal on the bitline on the selected memory cell side is read out by the senseamplifier.

[0102] In the third embodiment, as described above, the potential of theshared gate signal during standby is equal to the external power supplypotential. Therefore, the power consumed at boosted potential VPPgenerated by the VPP generating circuit can be reduced during standby.

[0103] [Fourth Embodiment]

[0104] According to a fourth embodiment, a control circuit 122 a is usedinstead of control circuit 122 in FIG. 11.

[0105]FIG. 14 is a circuit diagram showing a structure of controlcircuit 122 a of the fourth embodiment.

[0106] Referring to FIG. 14, control circuit 122 a includes a delaycircuit 152 which receives and delays block select signal BLKl by apredetermined time, an NOR circuit 154 which receives block selectsignal BLK1 and the output of delay circuit 152, a level convertingcircuit 156 which receives the output of NOR circuit 154, and convertsthe level thereof to issue control signal A, a level converting circuit158 which receives block select signal BLK2, and converts the levelthereof to issue control signal B, an inverter 160 which receives andinverts block select signal BLK2, an NAND circuit 162 which receives theoutputs of NOR circuit 154 and inverter 160, and a level convertingcircuit 164 which receives the output of NAND circuit 162, and issuescontrol signal C. In the fourth embodiment, control circuit 126 shown inFIG. 11 has the substantially same structure as that already describedwith reference to FIG. 14, and description thereof is not repeated.

[0107]FIG. 15 is an operation waveform diagram showing an operation ofthe three-state circuit provided with control circuit 122 a.

[0108] Referring to FIG. 15, block select signal BLKL rises from L-levelto H-level at time t1. Thereby, control signal CL rises from L-level toH-level, and P-channel MOS transistor 96 a in FIG. 96a is turned off.Also, control signal AL falls from H-level to L-level, and P-channel MOStransistor 92 is turned on. Therefore, shared gate signal BLIL issuedfrom the three-state circuit rises from external power supply potentialexvdd to boosted potential VPP. Control signal BR rises from L-level toH-level, and shared gate signal BLIR attains the ground potential sothat the gate circuit isolates block R from the sense amplifier.

[0109] At time t2, block select signal BLKL falls from H-level toL-level, and thereby control signal BR falls from H-level to L-level sothat shared gate signal BLIR rises from the ground potential to externalpower supply potential exvdd. In this case, shared gate signal BLIL iskept at boosted potential VPP. When a delay time Td elapses from timet2, control signal AL rises from L-level to H-level, and control signalCL falls from H-level to L-level. Thereby, shared gate signal BLILlowers from boosted potential VPP to external power supply potentialexvdd.

[0110] At time t3, block select signal BLKR rises from L-level toH-level, and thereby control signal BL rises from L-level to H-level sothat shared gate signal BLIL falls from external power supply potentialexvdd to the ground potential. Control signal AR falls from H-level toL-level, and control signal CR rises from L-level to H-level so thatshared gate signal BLIR rises from external power supply potential exvddto boosted potential VPP.

[0111] At time t4, block select signal BLKR falls from H-level toL-level. Thereby, control signal BL falls from H-level to L-level, andshared gate signal BLIL rises from the ground potential to externalpower supply potential exvdd. When delay time Td elapses from time t4,control signal AR rises from L-level to H-level, and control signal CRfalls from H-level to L-level so that shared gate signal BLIR lowersfrom boosted potential VPP to external power supply potential exvdd.

[0112]FIG. 16 is an operation waveform diagram showing a data readoperation in the fourth embodiment.

[0113] Referring to FIGS. 6 and 16, block select signal BLKL rises fromL-level to H-level at time t1. For reading out the data from the memorycell in block L, therefore, equalize signal BLEQL falls to L-level, andbit lines BLL and /BLL are released from the equalized state. Sharedgate signal BLIL attains boosted potential VPP, and bit lines BL and /BLare coupled to bit lines BLL and /BLL, respectively. Since shared gatesignal BLIR falls to the ground potential, bit lines BL and /BL areisolated from bit lines BLR and /BLR, respectively. Thereafter, wordline WL is activated, and the potential on the bit line changes fromequalized potential VBL in accordance with the data stored in memorycell MC. Sense amplifier 102 amplifies the potential difference occurredon the bit line pair so that data reading is performed.

[0114] When the read operation is completed at time t2, block selectsignal BLKL falls to L-level. Thereby, equalize signal BLEQL rises toH-level, and bit lines BLL and /BLL are set to equalized potential VBLagain. At this point of time, since shared gate signal BLIL is held atboosted potential VPP, bit lines BL and /BL are charged to potential VBLby equalize circuit 108. Therefore, gate circuit 104 is held in thestate providing a small on-resistance for a period of equalizing bitlines BL and /BL. Accordingly, the equalize time of bit lines BL and /BLcan be reduced from a conventional value of ΔtEQ1 to ΔtEQ2.

[0115] According to the semiconductor memory device of the fourthembodiment, as already described, the time required for equalizing bitlines BL and /BL connected to the sense amplifier is reduced by such amanner that the shared gate signal is held at the raised potential, andthereby the gate circuit is held in the state providing a smallon-resistance for a period equal to the predetermined delay time beforethe potential is externally restored to external power supply potentialexvdd during the standby. Accordingly, the equalize circuit arranged onthe memory cell side can rapidly charge the bit lines.

[0116] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor memory device comprising: amemory cell array including a plurality of memory cells arranged in rowsand columns for storing externally applied data; a voltage generatingcircuit for receiving and boosting an externally applied first powersupply potential to generate a second power supply potential to be usedfor data transmission with respect to said memory cell array; a firstinternal node being activated by said second power supply potential; afirst control circuit for issuing first and second control signals fordriving said first internal node in accordance with an externallyapplied input signal, said first control circuit activating said firstcontrol signal for a predetermined time in accordance with change insaid input signal, and activating said second control signal uponelapsing of said predetermined time after the change in said inputsignal; and a first drive circuit for receiving said first and secondpower supply potentials, and driving the potential on said firstinternal node to said second power supply potential in accordance withsaid first and second control signals, wherein said first drive circuitincludes: a first switch circuit to be turned on to couple said firstpower supply potential to said first internal node in accordance withsaid first control signal, and a second switch circuit to be turned onto couple said second power supply potential to said first internal nodein accordance with said second control signal.
 2. The semiconductormemory device according to claim 1 , wherein said input signal is a rowaddress signal; said semiconductor memory device further comprises: asecond control signal for generating third and fourth control signals inaccordance with said row address signals, and a second drive circuit forreceiving said first and second power supply potentials, and driving apotential on a second internal node to said second power supplypotential in accordance with said third and fourth control signals; andsaid memory cell array includes: first bit line pairs providedcorresponding to the columns of said memory cells, respectively, a senseamplifier for amplifying a potential difference on said first bit linepair, second and third bit line pairs commonly using said senseamplifier, a first gate circuit for connecting said first bit line pairto said second bit line pair in accordance with the potential on saidfirst internal node, and a second gate circuit for connecting said firstbit line pair to said third bit line pair in accordance with thepotential on said second internal node.
 3. The semiconductor memorydevice according to claim 2 , wherein said first gate circuit includes afirst pair of N-channel MOS transistors having gates connected to saidfirst internal node, and connected between said first bit line pair andsaid second bit line pair, and said second gate circuit has a secondpair of N-channel MOS transistors having gates connected to said secondinternal node, and connected between said first bit line pair and saidthird bit line pair.
 4. The semiconductor memory device according toclaim 1 , wherein said memory cell array includes: a bit line pairprovided corresponding to each of the columns of said memory cells, andhaving first and second bit lines, and an equalize circuit forequalizing the potentials on said first and second bit lines with eachother in accordance with the output of said first drive circuit.
 5. Thesemiconductor memory device according to claim 1 , wherein said firstswitch circuit has an N-channel MOS transistor to couple said firstpower supply potential to said first internal node, and having a gatereceiving said first control signal, and said first control circuitissues said second power supply potential as an activation potential ofsaid first control signal.
 6. The semiconductor memory device accordingto claim 1 , wherein said first switch circuit has a P-channel MOStransistor to couple said first power supply potential to said firstinternal node, and having a gate receiving said first control signal. 7.The semiconductor memory device according to claim 6 , wherein saidP-channel MOS transistor has a back gate coupled to said second powersupply potential.
 8. The semiconductor memory device according to claim6 , wherein said first control circuit issues said second power supplypotential as a deactivation potential of said first control signal, andissues the ground potential as an activation potential of said firstcontrol signal.
 9. A semiconductor memory device comprising: a memorycell array including a plurality of memory cells arranged in rows andcolumns for storing externally applied data; a voltage generatingcircuit for receiving and boosting an externally applied first powersupply potential to generate a second power supply potential to be usedfor data transmission with respect to said memory cell array; and afirst drive circuit for receiving said first and second power supplypotentials and a ground potential, and driving a potential on a firstinternal node in accordance with an externally applied input signal,said first drive circuit activating the potential on said first internalnode to attain said second power supply potential when said input signalindicates access to a first region in said memory cell array,deactivating the potential on said first internal node to attain saidground potential when said input signal indicates access to a secondregion in said memory cell array, and coupling the potential on saidfirst internal node to said first power supply potential when said inputsignal does not indicate the access to said memory cell array.
 10. Thesemiconductor memory device according to claim 9 , wherein said inputsignal is a row address signal, said first drive circuit is providedcorresponding to said first region, said semiconductor memory devicefurther comprises a second drive circuit provided corresponding to saidsecond region for driving said second internal node, and said seconddrive circuit activates the potential on said second internal node toattain said second power supply potential when said input signalindicates the access to the second region in said memory cell array,deactivates the potential on said second internal node to attain saidground potential when said input signal indicates the access to thefirst region in said memory cell array, and couples the potential onsaid second internal node to said first power supply potential when saidinput signal does not indicate the access to said memory cell array. 11.The semiconductor memory device according to claim 10 , wherein saidmemory cell array includes: a first bit line pair provided correspondingto each of the columns of said memory cells, a sense amplifier foramplifying a potential difference on said first bit line pair, secondand third bit line pairs commonly using said sense amplifier, andprovided for said first and second regions, respectively, a first gatecircuit for connecting said first bit line pair to said second bit linepair in accordance with the potential on said first internal node, and asecond gate circuit for connecting said first bit line pair to saidthird bit line pair in accordance with the potential on said secondinternal node.
 12. The semiconductor memory device according to claim 11, further comprising: a first control circuit for issuing first, secondand third control signals to control said first drive circuit inaccordance with said address signal, wherein said first control circuitoperates to activate said first control signal and deactivate saidsecond and third control signals when said address signal designate saidfirst region, operates to activate said second control signal anddeactivate said first and third control signals when said address signaldesignates said second region, and operates to activate said thirdcontrol signal and deactivate said first and second control signals whensaid address signal does not indicate the access to said memory cellarray; and said first drive circuit includes: a first switch circuit forcoupling said first internal node to said second power supply potentialin accordance with activation of said first control signal, a secondswitch circuit for coupling said first internal node to said groundpotential in accordance with activation of said second control signal,and a third switch circuit for coupling said first internal node to saidfirst power supply potential in accordance with activation of said thirdcontrol signal.
 13. The semiconductor memory device according to claim12 , wherein said memory array further includes an equalize circuitarranged in said first region for equalizing the potentials on saidsecond bit line pair when the access to said first region is notperformed, and said first control circuit deactivates said first controlsignal after a predetermined time from end of the access to said firstregion subsequent to designation of said first region by said addresssignal.